6.5080 Multicore Programming -

In 2005, Intel canceled the development of its 4GHz Pentium 4 chip, marking the definitive end of Dennard scaling. Since then, transistor density has continued to increase according to Moore’s Law, but clock speeds have stagnated. The industry’s response has been the multicore processor: chips containing two, four, sixty-four, or more distinct processing units. However, adding cores does not automatically accelerate software. As computer architect Herb Sutter famously noted, “The free lunch is over.” Course 6.5080 confronts this crisis directly. It transitions the student from thinking like a sequential programmer—where each step follows logically from the last—to thinking like a concurrent systems architect, where multiple threads of execution interleave, contend for memory, and must cooperate without corruption.

Before writing a single parallel loop, 6.5080 insists on understanding the hardware. Multicore processors do not provide a “perfectly simultaneous” view of memory. Instead, each core possesses private L1 and L2 caches, a shared L3 cache, and the main DRAM. This hierarchy introduces the problem of . The course covers the MESI (Modified, Exclusive, Shared, Invalid) protocol extensively. A student learns why two threads incrementing the same shared variable from different cores can miss each other’s updates, leading to lost counts. 6.5080 multicore programming

The most contemporary module covers (TM). Both hardware (HTM on Intel TSX) and software (STM) implementations are examined. Students write code where critical sections are marked as atomic transactions. The system optimistically executes the code and aborts if a conflict is detected. This dramatically simplifies reasoning (no deadlock, no lock ordering), but introduces new challenges: transaction size limits, irrevocable actions, and performance collapse under contention. Through benchmarking, the course concludes that while TM is not a universal silver bullet, it excels for complex composite operations (e.g., transferring money between two bank accounts) where fine-grained locking would be a nightmare. In 2005, Intel canceled the development of its